1. Field of the Invention
The present invention relates to a memory cell having a stacked structure and its method of manufacture and more particularly, to a dynamic random access memory (hereinafter DRAM) cell of a stacked structure having a cup shaped polysilicon storage electrode capable of being applied to 16 mega and 64 mega DRAM cells.
2. Description of the Prior Art
Conventionally, various types of semiconductor memory devices are well known in the art. In such semiconductor memory devices, it is a conventional situation that a 1 mega DRAM has already come to mass production, a 4 mega DRAM has come to pilot production, a 16 mega DRAM has come to being a new product, and a 64 mega DRAM is developing successively.
In order to develop such large quantity memory devices, fundamental techniques, such as lithographic techniques or thin film forming techniques, should be developed. The DRAM cell of fundamental element for the DRAM structure should also be developed.
According to such demands, the DRAM cell development has repeated many changes from a plane structure to a trench or a stacked structure, and it is being developed to maximize the area efficiency as far as possible under a condition that its method of manufacture is allowed.
Recently, the stacked structure of a highly integrated DRAM cell is preferred due to the ease of manufacture and immunity to the alpha particle.
In the process for manufacturing a conventional stacked type cell, as a limiting condition for increasing the area of the storage electrode, there are area and height characteristics of the storage electrode.
For the purpose of the contact of a bit line and a drain of a transfer transistor, the area of the capacitor cannot be increased up to more than a contacting region, and also when the storage electrode is raised up in order to increase the area of the storing electrode, difficulties may occur with respect to the contact of the bit line.
FIG. 1a shows a cross-sectional view of a conventional stack structure DRAM cell, wherein a storage node is raised up, and the bit line step coverage becomes worse. Since the bit line contacting area should be ensured, it cannot be expanded to more than the present storage electrode area.
FIG. 1b is a cross-sectional view of a DRAM cell disclosed by Mitsubishi Company of Japan and announced at the VLSI symposium in 1989, which is a stacked structure DRAM cell including a storage node pattern made to a cylindrical form whereby an interior and exterior of the cylinder is utilized as a charge storing capacitor.
This makes the electrode forming area large because the cylindrical type storage node is made by utilizing a polysilicon spacer so that thickness of the cylinder node can be formed to less than the minimum design rule.
However, when the storage node is raised up, the bit line step coverage causes a problem and the storage node cannot be extended laterally any more because of the bit line contact forming area. There is a disadvantage in that the cylindrical type node should be made sufficiently less than a polysilicon pad because of an overlay accuracy problem of the cylindrical type node and the polysilicon pad with respect to the node contact. Accordingly, a tungsten plug is used for the bit line contact and 30 fF of storing capacitor value is obtained by use of 5 nm of effective oxide film and 1.5 .mu.m in height of the storing electrode.
However, the DRAM cell of the above-described structure has problems in that its manufacturing process is complicated and the number of mask layers is increased.
FIG. 1c is a cross-sectional view of DASH (diagonal active stacked capacitor cell with a highly-packed storage node) cell of Hitachi Company of Japan, which is structured with an active region made to pass with an angle of 45 degrees to the bit line whereby the bit line is formed before the storing electrode and thereafter, the storage node is formed.
Since a method of forming the bit line is conducted previously, it may be an advantage that the storing electrode can be formed up to above the bit line contact region. However, the form of the storage node is not suitable for the DRAM cell of 64 mega class since the electrode of a conventionally existing stacked structure is used as it is.